1. Field of the Invention
This invention relates to analog and digital processors and methods, and more particularly to preview mode low resolution output systems and methods for charge coupled devices (CCDs), CMOS imagers, and cameras.
2. Description of the Related Art
Camera systems using charge coupled devices (CCDs) and imagers of many kinds are well-known for capturing signals according to many different CCD output formats and pixel configurations. According to one such format, in order to obtain a still image with acceptable resolution and contrast from a CCD, a minimum of 10 bits of resolution is desired. To practically capture a CCD image, the data read-out time from the CCD is very limited. Accordingly, one such front end interface which accepts CCD data for conversion into digital form operates typically up to 16 MHz with a 10-bit analog-to-digital converter. A, camera using this front-end can produce a digital still image with up to 8kxc3x978k pixels. The feature set available in known CCD camera systems is increasing to include more functionality, as well as extended dynamic range. Such extended functionality comes at a price in terms of electronic complexity and power consumption. For example, some current camera systems include a liquid crystal display (LCD) screen to enable viewing of images in a real-time viewfinder. This requires the CCD and associated processing chips to run in a video mode and to remain powered up while the screen is in use. This can dissipate a large amount of power that tends to shorten battery life. In such an operational mode, front end circuitry is operated at a resolution level which is unnecessary for driving the relatively low resolution LCD display, thereby consuming power needlessly.
Accordingly, there is a need to enable low power operation of the analog and digital subsystems in CCD camera and imager systems that convert analog data into digital signal forms for user applications. It is desirable to achieve lower power even at a sacrifice in resolution in the front end system.
According to one embodiment of the present invention, a processing system for an imager device includes a camera system for producing a desired imager signal which operates in a reduced power or preview mode. Such a system according to the present invention includes a correlated double sample (CDS) circuit for receiving data from a selected imager, a multi-mode (selectably high or low current) variable gain amplifier (VGA), a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said CDS circuit. The low power mode enables production of an ADC output signal of selectable higher or lower resolution. The processing system according to the present invention includes a gain adjust block (GAB) coupled to the ADC, a black level adjustment circuit including a predetermined clamp setting, a compander circuit coupled to said GAB for further reducing the output bit-width, a multiplexer permitting selection of output signals of selected bit-width, and a phase-lock-loop (PLL) for controlling a multi-sync timing generator including an analog clock generator (ACG). According to the present invention, the compander bit-width reduction compresses the output so a smaller bit-width signal can retain the same dynamic range as a larger bit-width signal, while the ADC output bit-width reduction sacrifices resolution. According to one embodiment of the present invention, by reducing the resolution requirement of the camera system front end to a selected number of bits during a still camera viewfinder video mode of operation, the power dissipated by the camera system is reduced substantially. In particular according to one embodiment of the present invention, a signal processing system (SPS) on an integrated substrate for a camera has a reduced power preview mode. The camera includes analog front-end (AFE) circuitry with digital outputs selectable for multiple bitwidths and having selectable high and low resolution (preview) output modes, and digital signal processing system (DSPS) circuitry connected to the analog front-end (AFE) circuitry. Further according to the present invention, a signal processing system (SPS) for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a multi-mode variable gain amplifier (VGA), a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said CDS circuit, a digital gain circuit (DGC) coupled to the ADC, and a compander circuit coupled to said DGC for further reducing the output bit-width of the camera system.